Reset and clock control (RCC) RM0008
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6.3.10 Control/status register (RCC_CSR)
Address: 0x24
Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Bit 2 LSEBYP External Low Speed oscillator Bypass
Set and reset by software to bypass oscillator in debug mode. This bit can be written only when the
external 32 kHz oscillator is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 1 LSERDY External Low Speed oscillator Ready
Set and reset by hardware to indicate when the external 32 kHz oscillator is stable. This bit needs 6
cycles of external Low Speed oscillator clock to fall down after LSEON reset.
0: External 32 kHz oscillator not ready
1: External 32 kHz oscillator ready
Bit 0 LSEON External Low Speed oscillator enable
Set and reset by software.
0: External 32 kHz oscillator OFF
1: External 32 kHz oscillator ON
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWR
RSTF
WWDG
RSTF
IWDG
RSTF
SFT
RSTF
POR
RSTF
PIN
RSTF
Res. RMVF Reserved
rw rw rw rw rw rw Res. rw Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
LSI
RDY
LSION
Res. r rw
Bit 31 LPWRRSTF Low-Power reset flag
Reset by software by writing the RMVF bit.
Set by hardware when a Low-power management reset occurs.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to Section : Low-power
management reset.
Bit 30 WWDGRSTF Window watchdog reset flag
Reset by software by writing the RMVF bit.
Set by hardware when a window watchdog reset occurs.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF Independent Watchdog reset flag
Reset by software by writing the RMVF bit.
Set by hardware when a watchdog reset from V
DD
domain occurs.
0: No watchdog reset occurred
1: Watchdog reset occurred
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