ST STM32F102 series User Manual

Reset and clock control (RCC) RM0008
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For further information on the User Option Bytes, refer to the STM32F10xxx Flash
programming manual.
6.1.2 Power reset
A power reset is generated when one of the following events occurs:
1. Power-on/power-down reset (POR/PDR reset)
2. When exiting Standby mode
A power reset sets all registers to their reset values except the Backup domain (see
Figure 4)
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address
0x0000_0004 in the memory map. For more
details, refer to Table 36: Vector table on page 123.
Figure 7. Reset circuit
The Backup domain has two specific resets that affect only the Backup domain (see
Figure 4).
6.1.3 Backup domain reset
A backup domain reset is generated when one of the following events occurs:
1. Software reset, triggered by setting the BDRST bit in the Backup domain control
register (RCC_BDCR).
2. V
DD
or V
BAT
power on, if both supplies have previously been powered off.
6.2 Clocks
Three different clock sources can be used to drive the system clock (SYSCLK):
● HSI oscillator clock
● HSE oscillator clock
● PLL clock
The devices have the following two secondary clock sources:
● 40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and
optionally the RTC used for Auto-wakeup from Stop/Standby mode.
● 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-
time clock (RTCCLK)
NRST
R
PU
V
DD
/V
DDA
WWDG Reset
IWDG Reset
Pulse
generator
Power Reset
External
Reset
(min 20 µs)
System Reset
Filter
Software Reset
Low-power management Reset

ST STM32F102 series Specifications

General

Brand	ST
Model	STM32F102 series
Category	Microcontrollers
Language	English