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Flexible static memory controller (FSMC) RM0008

382/690

Mode C - NOR Flash - OE toggling

Figure 166. ModeC read accesses

Figure 167. ModeC write accesses

The differences compared with mode1 are the toggling of NOE and NADV and the

independent read and write timings.

A[25:0]

NOE

(ADDSET +1) (DATAST + 1)

Memory transaction

Data strobe

NEx

D[15:0]

HCLK cycles HCLK cycles

NWE

NADV

data driven

by memory

ai14725c

High

2 HCLK

cycles

Data sampled

A[25:0]

NOE

(ADDSET +1) (DATAST + 1)

Memory transaction

NEx

D[15:0]

HCLK cycles HCLK cycles

NWE

NADV

data driven by FSMC

ai14723b

1HCLK

Default Chapter2
- Table of Contents2
Documentation Conventions32
- List of Abbreviations for Registers32
- Glossary32
- Peripheral Availability32
Memory and Bus Architecture33
- System Architecture33
- Figure 1. System Architecture33
- Memory Organization34
- Memory Map35
- Boot Configuration43
- Table 5. Boot Modes43
CRC Calculation Unit44
- Introduction44
- CRC Main Features44
- Figure 3. CRC Calculation Unit Block Diagram44
- CRC Functional Description45
- CRC Registers45
Power Control (PWR)48
- Power Supplies48
- Power Supply Supervisor50
- Low-Power Modes52
- Power Control Registers57
Backup Registers (BKP)61
- BKP Introduction61
- BKP Main Features61
- BKP Functional Description62
  - Tamper Detection62
  - RTC Calibration62
- BKP Registers63
Reset and Clock Control (RCC)69
- Reset69
- Clocks70
- RCC Registers77
General-Purpose and Alternate-Function I/Os (Gpios and Afios)97
- GPIO Functional Description97
- GPIO Registers105
- Alternate Function I/O and Debug Configuration (AFIO)110
- AFIO Registers115
- GPIO and AFIO Register Maps121
- Table 34. GPIO Register Map and Reset Values121
- Table 35. AFIO Register Map and Reset Values122
Interrupts and Events123
- Nested Vectored Interrupt Controller (NVIC)123
- External Interrupt/Event Controller (EXTI)126
- EXTI Registers130
DMA Controller (DMA)134
- Introduction134
- DMA Main Features134
- DMA Functional Description135
- DMA Registers142
Analog-To-Digital Converter (ADC)149
- Introduction149
- ADC Main Features149
- ADC Functional Description150
  - Figure 21. Single ADC Block Diagram150
  - ADC Clock151
  - ADC On-Off Control151
  - Channel Selection151
  - Table 42. ADC Pins151
  - Continuous Conversion Mode152
  - Single Conversion Mode152
  - Timing Diagram152
  - Analog Watchdog153
  - Figure 22. Timing Diagram153
  - Figure 23. Analog Watchdog Guarded Area153
  - Table 43. Analog Watchdog Channel Selection153
  - Injected Channel Management154
  - Scan Mode154
  - Discontinuous Mode155
  - Figure 24. Injected Conversion Latency155
- Calibration156
- Data Alignment156
- Figure 25. Calibration Timing Diagram156
- Channel-By-Channel Programmable Sample Time157
- Conversion on External Trigger157
- Figure 26. Right Alignment of Data157
- Figure 27. Left Alignment of Data157
- Table 44. External Trigger for Regular Channels for ADC1 and ADC2158
- Table 45. External Trigger for Injected Channels for ADC1 and ADC2158
- DMA Request159
- Table 46. External Trigger for Regular Channels for ADC3159
- Table 47. External Trigger for Injected Channels for ADC3159
- Dual ADC Mode160
  - Figure 28. Dual ADC Block Diagram161
  - Figure 29. Injected Simultaneous Mode on 4 Channels162
  - Injected Simultaneous Mode162
  - Regular Simultaneous Mode162
  - Fast Interleaved Mode163
  - Figure 30. Regular Simultaneous Mode on 16 Channels163
  - Figure 31. Fast Interleaved Mode on 1 Channel in Continuous Conversion Mode163
  - Slow Interleaved Mode163
  - Alternate Trigger Mode164
  - Figure 32. Slow Interleaved Mode on 1 Channel164
  - Figure 33. Alternate Trigger: Injected Channel Group of each ADC164
  - Combined Regular Simultaneous + Alternate Trigger Mode165
  - Combined Regular/Injected Simultaneous Mode165
  - Figure 34. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Model165
  - Independent Mode165
  - Combined Injected Simultaneous + Interleaved166
  - Figure 35. Alternate + Regular Simultaneous166
  - Figure 36. Case of Trigger Occurring During Injected Conversion166
  - Figure 37. Interleaved Single Channel with Injected Sequence CH11, CH12166
- Temperature Sensor167
- Figure 38. Temperature Sensor and VREFINT Channel Block Diagram167
- ADC Interrupts168
- Table 48. ADC Interrupts168
- ADC Registers169
  - ADC Status Register (ADC_SR)169
  - ADC Control Register 1 (ADC_CR1)170
  - ADC Control Register 2 (ADC_CR2)172
  - ADC Sample Time Register 1 (ADC_SMPR1)175
  - ADC Sample Time Register 2 (ADC_SMPR2)176
  - ADC Injected Channel Data Offset Register X (Adc_Jofrx)(X=1176
  - ADC Watchdog High Threshold Register (ADC_HTR)177
  - ADC Watchdog Low Threshold Register (ADC_LTR)177
  - ADC Regular Sequence Register 1 (ADC_SQR1)178
  - ADC Regular Sequence Register 2 (ADC_SQR2)178
  - ADC Regular Sequence Register 3 (ADC_SQR3)179
  - ADC Injected Sequence Register (ADC_JSQR)180
  - ADC Injected Data Register X (Adc_Jdrx) (X= 1181
  - ADC Regular Data Register (ADC_DR)181
  - 10.12.15 ADC Register Map182
  - Table 49. ADC - Register Map and Reset Values182
Digital-To-Analog Converter (DAC)184
- Introduction184
- DAC Main Features184
- Table 50. DAC Pins185
- Figure 39. DAC Channel Block Diagram185
- DAC Functional Description186
- Dual DAC Channel Conversion191
- DAC Registers196
Advanced-Control Timers (TIM1&TIM8)206
- TIM1&TIM8 Introduction206
- TIM1&TIM8 Main Features206
- Figure 47. Advanced-Control Timer Block Diagram208
- TIM1&TIM8 Functional Description209
- TIM1&TIM8 Registers247
General-Purpose Timer (Timx)273
- Introduction273
- Timx Main Features274
- Timx Functional Description275
- Timx Registers310
Basic Timer (TIM6&7)330
- Introduction330
- TIM6&TIM7 Main Features330
- TIM6&TIM7 Functional Description331
- TIM6&TIM7 Registers336
Real-Time Clock (RTC)342
- RTC Introduction342
- RTC Main Features343
- RTC Functional Description343
- RTC Registers347
Independent Watchdog (IWDG)354
- Introduction354
- IWDG Main Features354
- IWDG Functional Description354
- IWDG Registers356
Window Watchdog (WWDG)360
- Introduction360
- WWDG Main Features360
- WWDG Functional Description360
- Figure 155. Watchdog Block Diagram361
- How to Program the Watchdog Timeout362
- Figure 156. Window Watchdog Timing Diagram362
- Debug Mode363
- Debug Registers363
Flexible Static Memory Controller (FSMC)365
- FSMC Main Features365
- Block Diagram366
- Figure 157. FSMC Block Diagram366
- AHB Interface367
  - Supported Memories and Transactions367
- External Device Address Mapping368
- NOR Flash/Psram Controller370
- NAND Flash/Pc Card Controller398
SDIO Interface (SDIO)412
- SDIO Main Features412
- SDIO Bus Topology413
- Figure 176. SDIO "No Response" and "No Data" Operations413
- Figure 177. SDIO (Multiple) Block Read Operation413
- Figure 178. SDIO (Multiple) Block Write Operation414
- Figure 179. SDIO Sequential Read Operation414
- Figure 180. SDIO Sequential Write Operation414
- SDIO Functional Description415
- Card Functional Description427
- Response Formats446
- SDIO I/O Card-Specific Operations450
- CE-ATA Specific Operations451
- HW Flow Control452
- SDIO Registers452
USB Full Speed Device Interface (USB)468
- Introduction468
- USB Main Features468
- USB Functional Description468
  - Figure 189. USB Peripheral Block Diagram469
  - Description of USB Blocks470
- Programming Considerations471
- USB Registers483
Controller Area Network (Bxcan)499
- Introduction499
- Bxcan Main Features499
- Bxcan Operating Modes502
- Bxcan Functional Description505
- Bxcan Interrupts516
- Figure 204. CAN Frames516
- Figure 205. Event Flags and Interrupt Generation517
- CAN Registers518
Serial Peripheral Interface (SPI)543
- SPI Introduction543
- SPI and I S Main Features544
  - SPI Features544
  - I 2 S Features545
- SPI Functional Description546
- I 2 S Functional Description555
- SPI and I S Registers569
Inter-Integrated Circuit (I 2 C) Interface580
- Introduction580
- I 2 C Main Features580
- I 2 C Functional Description581
- I 2 C Interrupts595
- Table 150. I2C Interrupt Requests595
- I 2 C Debug Mode596
- I 2 C Registers596
Universal Synchronous Asynchronous Receiver Transmitter (USART)610
- Introduction610
- USART Main Features610
- USART Functional Description611
- USART Interrupts637
- Table 155. USART Interrupt Requests637
- USART Mode Configuration638
- USART Registers638
Device Electronic Signature650
- Memory Size Registers650
  - Flash Size Register650
- Unique Device ID Register (96 Bits)651
Debug Support (DBG)653
- Overview653
- Figure 258. Block Diagram of Stm32F10Xxx-Level and Cortex-M3-Level Debug Support654
- Reference ARM Documentation655
- SWJ Debug Port (Serial Wire and JTAG)655
  - Mechanism to Select the JTAG-DP or the SW-DP655
  - Figure 259. SWJ Debug Port655
- Pinout and Debug Port Pins656
  - SWJ Debug Port Pins656
  - Flexible SWJ-DP Pin Assignment656
  - Table 158. SWJ Debug Port Pins656
  - Internal Pull-Up and Pull-Down on JTAG Pins657
  - Table 159. Flexible SWJ-DP Pin Assignment657
  - Using Serial Wire and Releasing the Unused Debug Pins as Gpios658
- Stm32F10Xxx JTAG TAP Connection658
- ID Codes and Locking Mechanism659
  - MCU Device ID Code659
  - Figure 260. JTAG TAP Connections659
  - Boundary Scan TAP660
  - Cortex-M3 TAP660
  - Cortex-M3 JEDEC-106 ID Code660
- JTAG Debug Port661
- Table 160. JTAG Debug Port Data Registers661
- SW Debug Port662
  - SW Protocol Introduction662
  - SW Protocol Sequence662
  - Table 161. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]662
  - SW-DP State Machine (Reset, Idle States, ID Code)663
  - Table 162. Packet Request (8-Bits)663
  - Table 163. ACK Response (3 Bits)663
  - Table 164. DATA Transfer (33 Bits)663
  - DP and AP Read/Write Accesses664
  - SW-DP Registers664
  - Table 165. SW-DP Registers664
  - SW-AP Registers665
- AHB-AP (AHB Access Port) - Valid for both JTAG-DP or SW-DP665
- Core Debug666
- Table 166. Cortex-M3 AHB-AP Registers666
- Table 167. Core Debug Registers666
- Capability of the Debugger Host to Connect under System Reset667
- FPB (Flash Patch Breakpoint)667
- DWT (Data Watchpoint Trigger)668
- ITM (Instrumentation Trace Macrocell)668
  - General Description668
  - Timestamp Packets, Synchronization and Overflow Packets668
  - Table 168. Main ITM Registers669
- MCU Debug Component (MCUDBG)670
  - Debug Support for Low-Power Modes670
  - Debug Support for Timers, Watchdog, Bxcan and I C670
  - Debug MCU Configuration Register671
- TPIU (Trace Port Interface Unit)673
  - Introduction673
  - TRACE Pin Assignment673
  - Table 169. Asynchronous TRACE Pin Assignment673
  - Figure 261. TPIU Block Diagram673
  - Table 170. Synchronous TRACE Pin Assignment674
  - Table 171. Flexible TRACE Pin Assignment674
  - TPUI Formatter675
  - TPUI Frame Synchronization Packets676
  - Emission of Synchronization Frame Packet676
  - Synchronous Mode676
  - Asynchronous Mode677
  - TRACECLKIN Connection Inside Stm32F10Xxx677
  - TPIU Registers677
  - Table 172. Important TPIU Registers677
  - 26.16.10 Example of Configuration678
- DBG Register Map679
- Table 173. DBG - Register Map and Reset Values679
- Table 174. Document Revision History680
- Figure 76. Output Stage of Capture/Compare Channel (Channel 4)680
- Figure 80. Center-Aligned PWM Waveforms (ARR=8)681
- Figure 109. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6681
- Figure 237. USART Block Diagram682
- Figure 86. 6-Step Generation, COM Example (OSSR=1)683
- Figure 95. General-Purpose Timer Block Diagram684
- Figure 257. USART Interrupt Mapping Diagram686
- Figure 229. I688

Brand	ST
Model	STM32F102 series
Category	Microcontrollers
Language	English

ST STM32F102 series User Manual

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