Independent watchdog (IWDG) RM0008
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The LSI can be calibrated so as to compute the IWDG timeout with an acceptable accuracy.
For more details refer to LSI calibration on page 74.
16.4 IWDG registers
Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions.
16.4.1 Key register (IWDG_KR)
Address offset: 0x00
Reset value: 0x0000 0000 (reset by Standby mode)
16.4.2 Prescaler register (IWDG_PR)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY[15:0]
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Bits 31:16 Reserved, read as 0.
Bits 15:0 KEY[15:0]: Key value (write only, read 0000h)
These bits must be written by software at regular intervals with the key value AAAAh, otherwise the
watchdog generates a reset when the counter reaches 0.
Writing the key value 5555h to enables access to the IWDG_PR and IWDG_RLR registers (see
Section 16.3.2)
Writing the key value CCCCh starts the watchdog (except if the hardware watchdog option is
selected)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved PR[2:0]
rw rw rw
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