Revision history RM0008
686/690
28-Jul-2008 5
Developed polynomial form updated in Section 3.2: CRC main features on
page 44.
Figure 4: Power supply overview on page 48 modified.
Section 4.1.2: Battery backup domain on page 49 modified.
Section 6.2.5: LSI clock on page 74 specified.
Section 7.1.4: Alternate functions (AF) on page 100 clarified.
Note added to Table 27: Timer 2 alternate function remapping on page 113.
Bits are write-only in Section 9.4.2: DMA interrupt flag clear register
(DMA_IFCR) on page 143.
Register name modified in Section 10.3.1: ADC on-off control on page 151.
Recommended sampling time given in Section 10.10: Temperature sensor
on page 167.
Bit attributes modified in Section 10.12.1: ADC status register (ADC_SR) on
page 169.
Note modified for bits 23:0 in Section 10.12.4: ADC sample time register 1
(ADC_SMPR1) on page 175.
Note added in Section 11.2: DAC main features on page 184.
Formula updated in Section 11.3.5: DAC output voltage on page 188.
DBL[4:0] description modified in Section 12.3.19: TIMx and external trigger
synchronization on page 243.
Figure 77 on page 226 and Figure 123 on page 291 modified.
Section 22.5.3: SPI status register (SPI_SR) on page 573 modified.
Closing the communication on page 588 updated.
Notes added to Section 23.6.8: Clock control register (I2C_CCR) on
page 606. TCK replaced by T
PCLK1
in Section 23.6.8 and Section 23.6.9.
OVR changed to ORE in Figure 257: USART interrupt mapping diagram on
page 637.
Section 24.6.1: Status register (USART_SR) on page 638 updated.
Slave select (NSS) pin management on page 547 clarified.
Small text changes.
Table 174. Document revision history (continued)
Date Revision Changes
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