RM0008 Revision history
687/690
26-Sep-2008 6
This reference manual also applies to low-density STM32F101xx,
STM32F102xx and STM32F103xx devices, and to medium-density
STM32F102xx devices. In all sections, definitions of low-density and
medium-density devices updated.
Section 1.3: Peripheral availability on page 32 added.
Section 2.3.4: Embedded Flash memory on page 39 updated. Section 4.1.2:
Battery backup domain on page 49 modified. Reset value of Port input data
register (GPIOx_IDR) (x=A..G) on page 107 modified. Note added in
Section 7.4: AFIO registers on page 115. Note removed from bits 18:0
description in Section 8.3.6: Pending register (EXTI_PR) on page 132.
Section 12.2: TIM1&TIM8 main features on page 206 and Section 13.2:
TIMx main features on page 274 updated. In Section 13.3.15: Timer
synchronization on page 304, TS=000.
FSMC_CLK signal direction corrected in Figure 157: FSMC block diagram
on page 366. “Feedback clock” paragraph removed from Section 18.5.3:
General timing rules on page 374.
In Section 18.5.6: NOR/PSRAM controller registers on page 393: reset
value modified, WAITEN bit default value after reset is 1, bits [5:6] definition
modified, , FACCEN default value after reset specified. NWE signal behavior
corrected in Figure 173: Synchronous write mode - PSRAM (CRAM) on
page 391. The FSMC interface does not support COSMO RAM and
OneNAND devices, and it does not support the asynchronous wait feature.
SRAM and ROM 32 memory data size removed from Table 74: NOR
Flash/PSRAM supported memories and transactions on page 373.
Data latency versus NOR Flash latency on page 388 modified. Bits 19:16
bits are reserved in SRAM/NOR-Flash write timing registers 1..4
(FSMC_BWTR1..4) on page 397.
Section 18.6.3: Timing diagrams for NAND, ATA and PC Card on page 401
modified.Definition of PWID bits modified in Section 18.6.6: NAND Flash/PC
Card controller registers on page 405. Section 18.6.5: Error correction code
computation ECC (NAND Flash) on page 405 modified.
Interrupt Mapper definition modified in Section 20.3.1: Description of USB
blocks on page 470. USB register and memory base addresses modified in
Section 20.5: USB registers on page 483.
Section 23.3.8: Packet error checking on page 594 modified.
Section : Start bit detection on page 617 added. PE bit description specified
in Status register (USART_SR) on page 638.
“RAM size register” section removed from Section 25: Device electronic
signature on page 650. Bit definitions updated in FIFO status and interrupt
register 2..4 (FSMC_SR2..4) on page 407.
Small text changes.
Table 174. Document revision history (continued)
Date Revision Changes
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