Flexible static memory controller (FSMC) RM0008
398/690
18.6 NAND Flash/PC Card controller
The FSMC generates the appropriate signal timings to drive the following types of device:
● NAND Flash
–8-bit
– 16-bit
● PC Card 16 compatible devices
The NAND/PC Card controller can control three external banks. Bank 2 and bank 3 support
NAND Flash devices. Bank 4 supports PC Card devices.
Each bank is configured by means of dedicated registers (Section 18.6.6). The
programmable memory parameters include access timings (shown in Table 9 5 ) and ECC
configuration.
Bits 15:8 DATAST: Data-phase duration.
These bits are written by software to define the duration of the data phase (refer to Figure 157 to
Figure 169), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses:
0000 0000: DATAST phase duration = 1 × HCLK clock cycle
...
0000_1111: DATAST phase duration = 16 × HCLK clock cycles (default value after reset)
Bits 7:4 ADDHLD: Address-hold phase duration.
These bits are written by software to define the duration of the address hold phase (refer to
Figure 166 to Figure 169), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash
accesses:
0000: ADDHLD phase duration = 1 × HCLK clock cycle -->
...
1111: ADDHLD phase duration = 16 × HCLK clock cycles (default value after reset)
Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always
1 Flash clock period duration.
Bits 3:0 ADDSET: Address setup phase duration.
These bits are written by software to define the duration of the address setup phase in HCLK
cycles (refer to Figure 166 to Figure 169), used in SRAMs, ROMs and asynchronous multiplexed
NOR Flash:
0000: ADDSET phase duration = 1 × HCLK clock cycle
...
1111: ADDSET phase duration = 16 × HCLK clock cycles (default value after reset)
Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always
1 Flash clock period duration.
To Next Page
Loading...
Need help?
General
