RM0008 Memory and bus architecture
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2 Memory and bus architecture
2.1 System architecture
The main system consists of:
● Five masters:
– Cortex™-M3 core ICode bus (I-bus), DCode bus (D-bus), and System bus (S-bus)
– GP-DMA1 & 2 (general-purpose DMA)
● Three slaves:
– Internal SRAM
– Internal Flash memory
– AHB to APB bridges (AHB2APBx) which connect all the APB peripherals
These are interconnected using a multilayer AHB bus architecture as shown in Figure 1:
Figure 1. System architecture
ICode bus
This bus connects the Instruction bus of the Cortex™-M3 core to the Flash memory
instruction interface. Prefetching is performed on this bus.
FLITF
Ch.1
Ch.2
Ch.7
Cortex-M3
DMA1
ICode
DCode
System
AHB system bus
DMA Request
APB1
Flash
Bridge 2
Bridge 1
Ch.1
Ch.2
Ch.5
DMA2
SRAM
FSMC
SDIO
APB2
DMA request
ADC3
GPIOC
USART1
TIM8
SPI1
TIM1
ADC2
ADC1
GPIOG
GPIOF
GPIOE
GPIOD
GPIOB
GPIOA
EXTI
AFIO
DAC SPI3/I2S
TIM2
PWR
BKP
bxCAN
USB
I2C2
I2C1
UART5
UART4
USART3
USART2
SPI2/I2S
IWDG
WWDG
RTC
TIM7
TIM6
TIM5
TIM4
TIM3
ai14800b
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