RM0008 Flexible static memory controller (FSMC)
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STARTAD[24:17] and finally STARTAD[25] for 64 Mb x 8 bit NAND Flash) in the
common memory or attribute space. The ALE input of the NAND Flash device is active
during the write strobe (low pulse on NWE), thus the written bytes are interpreted as
the start address for read operations. Using the attribute memory space makes it
possible to use a different timing configuration of the FSMC, which can be used to
implement the prewait functionality needed by some NAND Flash memories (see
details in Section 18.6.4: NAND-Flash ready/busy management on page 403).
4. The controller waits for the NAND Flash to be ready (R/NB signal high) to become
active, before starting a new access (to same or another memory bank). While waiting,
the controller maintains the NCE signal active (low).
5. The CPU can then perform byte read operations in the common memory space to read
the NAND Flash page (data field + Spare field) byte by byte.
6. The next NAND Flash page can be read without any CPU command or address write
operation, in three different ways:
– by simply performing the operation described in step 5
– a new random address can be accessed by restarting the operation at step 3
– a new command can be sent to the NAND Flash device by restarting at step 2
18.6.4 NAND-Flash ready/busy management
Some NAND Flash devices require that the NCE signal stays low after the last address input
and during the Busy state (R/NB pin low) for correct operation, as shown in Figure 175.
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