RM0008 Flexible static memory controller (FSMC)
389/690
Figure 172. Synchronous read mode - NOR, PSRAM (CRAM)
1. Byte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held
low.
Addr[15:0] data data data data
addr[25:16]
Memory transaction = burst of 4 half words
HCLK
CLK
A[25:16]
NEx
NOE
NWE
High
NADV
NWAIT
(WAITCFG = 0)
NWAIT
(WAITCFG = 1)
A/D[15:0]
1 clock
cycle
1 clock
cycle
DATALAT CLK cycles inserted wait state
Data strobes
Data strobes
ai14730
Table 91. FSMC_BCRx bit fields
Bit No. Bit name Value to set
31-20 0x0000
19 CBURSTRW No effect on synchronous read
18-15 0x0
14 EXTMOD 0x0
13 WAITEN
When high, the first data after latency period is taken as always
valid, regardless of the wait from memory value
12 WREN no effect on synchronous read
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