RM0008 Flexible static memory controller (FSMC)
391/690
Figure 173. Synchronous write mode - PSRAM (CRAM)
1. Memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.
2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.
Addr[15:0] data data data data
addr[25:16]
Memory transaction = burst of 4 half words
HCLK
CLK
A[25:16]
NEx
NOE
NWE
NADV
NWAIT
(WAITCFG = 0)
A/D[15:0]
1 CLK
cycle
1 CLK
cycle
DATALAT CLK cycles inserted wait state
ai14731c
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