RM0008 Advanced-control timers (TIM1&TIM8)
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Bit 5 COMIF: COM interrupt Flag.
This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE,
OCxM - have been updated). It is cleared by software.
0: No COM event occurred.
1: COM interrupt pending.
Bit 4 CC4IF: Capture/Compare 4 interrupt Flag.
refer to CC1IF description
Bit 3 CC3IF: Capture/Compare 3 interrupt Flag.
refer to CC1IF description
Bit 2 CC2IF: Capture/Compare 2 interrupt Flag.
refer to CC1IF description
Bit 1 CC1IF: Capture/Compare 1 interrupt Flag.
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some exception in
center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by
software.
0: No match.
1: The content of the counter TIMx_CNT has matched the content of the TIMx_CCR1 register.
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1
register.
0: No input capture occurred.
1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1
which matches the selected polarity).
Bit 0 UIF: Update interrupt Flag.
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow or underflow regarding the repetition counter value (update if REP_CNT=0) and if the
UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and
UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by a trigger event (refer to Section 12.4.3: Slave mode control register
(TIMx_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
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