ST STM32F102 series User Manual

RM0008 Inter-integrated circuit (I
2
C) interface
607/690
Bit 14 DUTY Fast Mode Duty Cycle
0: Fast Mode t
low
/t
high
= 2
1: Fast Mode t
low
/t
high
= 16/9 (see CCR)
Bits 13:12 Reserved, forced by hardware to 0.
Bits 11:0 CCR[11:0] Clock Control Register in Fast/Standard mode (Master mode)
Controls the SCL clock in master mode.
Standard Mode or SMBus
:
T
high
= CCR * T
PCLK1
T
ow
= CCR * T
PCLK1
Fast Mode:
If DUTY = 0:
T
high
= CCR * T
PCLK1
T
ow
= 2 * CCR * T
PCLK1
If DUTY = 1: (to reach 400 kHz)
T
high
= 9 * CCR * T
PCLK1
T
ow
= 16 * CCR * T
PCLK1
For instance: in standard mode, to generate a 100 kHz SCL frequency:
If FREQR = 08, T
PCLK1
= 125 ns so CCR must be programmed with 0x28
(0x28 <=> 40d x 125 ns = 5000 ns.)
Notes:
1. The minimum allowed value is 0x04, except in FAST DUTY mode where the minimum allowed value
is 0x01
2. t
high
includes the SCLH rising edge
3. t
low
includes the SCLH falling edge
4. These timings are without filters.
5. The CCR register must be configured only when the I
2
C is disabled (PE = 0).
6. f
CK
= a multiple of 10 MHz is required to generate the fast clock at 400 kHz.

ST STM32F102 series Specifications

General

Brand	ST
Model	STM32F102 series
Category	Microcontrollers
Language	English