ST STM32F102 series User Manual

RM0008 Advanced-control timers (TIM1&TIM8)
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Bits 11:8 ETF[3:0]: External trigger filter.
This bit-field then defines the frequency used to sample ETRP signal and the length of the digital
filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to
validate a transition on the output:
0000: No filter, sampling is done at f
DTS
.
0001: f
SAMPLING
=f
CK_INT
, N=2.
0010: f
SAMPLING
=f
CK_INT
, N=4.
0011: f
SAMPLING
=f
CK_INT
, N=8.
0100: f
SAMPLING
=f
DTS
/2, N=6.
0101: f
SAMPLING
=f
DTS
/2, N=8.
0110: f
SAMPLING
=f
DTS
/4, N=6.
0111: f
SAMPLING
=f
DTS
/4, N=8.
1000: f
SAMPLING
=f
DTS
/8, N=6.
1001: f
SAMPLING
=f
DTS
/8, N=8.
1010: f
SAMPLING
=f
DTS
/16, N=5.
1011: f
SAMPLING
=f
DTS
/16, N=6.
1100: f
SAMPLING
=f
DTS
/16, N=8.
1101: f
SAMPLING
=f
DTS
/32, N=5.
1110: f
SAMPLING
=f
DTS
/32, N=6.
1111: f
SAMPLING
=f
DTS
/32, N=8.
Bit 7 MSM: Master/slave mode.
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization
between the current timer and its slaves (through TRGO). It is useful if we want to synchronize
several timers on a single external event.

ST STM32F102 series Specifications

General

Brand	ST
Model	STM32F102 series
Category	Microcontrollers
Language	English