ST STM32F102 series

RM0008 Advanced-control timers (TIM1&TIM8)
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Figure 63. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
Figure 64. Counter timing diagram, internal clock divided by N
Figure 65. Counter timing diagram, update event with ARPE=1 (counter underflow)
CK_PSC
0036 0035
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
0034
0035
Counter overflow
Update event (UEV)
Note: Here, center-aligned mode 2 or 3 is used with an UIF on overflow
Timer clock = CK_CNT
Counter register
00
20
1F
Update interrupt flag (UIF)
Counter underflow
Update event (UEV)
CK_PSC
01
CK_PSC
00
CEN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter underflow
Update event (UEV)
01 02 03 04 05 06 0705 04 03 02 0106
Auto-reload preload register
FD 36
Write a new value in TIMx_ARR
Auto-reload active register
FD 36