ST STM32F102 series User Manual

RM0008 Memory and bus architecture
37/690
0x4000 7800 - 0x4000 FFFF Reserved
APB1
0x4000 7400 - 0x4000 77FF DAC
Section 11.5.14 on page
205
0x4000 7000 - 0x4000 73FF Power control PWR Section 4.4.3 on page 60
0x4000 6C00 - 0x4000 6FFF Backup registers (BKP) Section 5.4.5 on page 66
0x4000 6800 - 0x4000 6BFF Reserved
0x4000 6400 - 0x4000 67FF bxCAN
Section 21.6.5 on page
537
0x4000 6000 - 0x4000 63FF
Shared USB/CAN SRAM 512
bytes
0x4000 5C00 - 0x4000 5FFF USB Registers
Section 20.5.4 on page
497
0x4000 5800 - 0x4000 5BFF I2C2
Section 23.6.10 on page
609
0x4000 5400 - 0x4000 57FF I2C1
Section 23.6.10 on page
609
0x4000 5000 - 0x4000 53FF UART5
Section 24.6.8 on page
649
0x4000 4C00 - 0x4000 4FFF UART4
Section 24.6.8 on page
649
0x4000 4800 - 0x4000 4BFF USART3
Section 24.6.8 on page
649
0x4000 4400 - 0x4000 47FF USART2
Section 24.6.8 on page
649
0x4000 4000 - 0x4000 3FFF Reserved
0x4000 3C00 - 0x4000 3FFF SPI3/I2S Section 22.5 on page 569
0x4000 3800 - 0x4000 3BFF SPI2/I2S Section 22.5 on page 569
0x4000 3400 - 0x4000 37FF Reserved
0x4000 3000 - 0x4000 33FF Independent watchdog (IWDG)
Section 16.4.5 on page
359
0x4000 2C00 - 0x4000 2FFF Window watchdog (WWDG)
Section 17.6.4 on page
364
0x4000 2800 - 0x4000 2BFF RTC
Section 15.4.7 on page
353
0x4000 1800 - 0x4000 27FF Reserved
0x4000 1400 - 0x4000 17FF TIM7 timer
Section 14.4.9 on page
341
0x4000 1000 - 0x4000 13FF TIM6 timer
Section 14.4.9 on page
341
0x4000 0C00 - 0x4000 0FFF TIM5 timer
Section 13.4.19 on page
328
Table 1. Register boundary addresses (continued)
Boundary address Peripheral Bus Register map

ST STM32F102 series Specifications

General

Brand	ST
Model	STM32F102 series
Category	Microcontrollers
Language	English