RM0008 Controller area network (bxCAN)
529/690
TX mailbox identifier register (CAN_TIxR) (x=0..2)
Address offsets: 0x180, 0x190, 0x1A0
Reset value: 0xXX where X is undefined (except bit 0, TXRQ = 0)
Note: 1 All TX registers are write protected when the mailbox is pending transmission (TMEx reset).
2 This register also implements the TX request control (bit 0) - reset value 0.
Mailbox data length control and time stamp register (CAN_TDTxR) (x=0..2)
All bits of this register are write protected when the mailbox is not in empty state.
Address offsets: 0x184, 0x194, 0x1A4
Reset value: 0xXX where X is undefined
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID[10:0]/EXID[28:18] EXID[17:13]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
EXID[12:0] IDE RTR TXRQ
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:21 STID[10:0]/EXID[28:18]: Standard Identifier or Extended Identifier
The standard identifier or the MSBs of the extended identifier (depending on the IDE bit value).
Bit 20:3 EXID[17:0:] Extended Identifier
The LSBs of the extended identifier.
Bit 2 IDE: Identifier Extension
This bit defines the identifier type of message in the mailbox.
0: Standard identifier.
1: Extended identifier.
Bit 1 RTR: Remote Transmission Request
0: Data frame
1: Remote frame
Bit 0 TXRQ: Transmit Mailbox Request
Set by software to request the transmission for the corresponding mailbox.
Cleared by hardware when the mailbox becomes empty.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Reserved TGT Reserved DLC[3:0]
Res. rw Res. rw rw rw rw
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