ST STM32F102 series

RM0008 Serial peripheral interface (SPI)
571/690
Bit 6 SPE: SPI Enable
0: Peripheral disabled
1: Peripheral enabled
Note: Not used in I
2
S mode
Bits 5:3 BR[2:0]: Baud Rate Control
000: f
PCLK
/2
001: f
PCLK
/4
010: f
PCLK
/8
011: f
PCLK
/16
100: f
PCLK
/32
101: f
PCLK
/64
110: f
PCLK
/128
111: f
PCLK
/256
Notes: These bits should not be changed when communication is ongoing.
Not used in I
2
S mode
Bit 2 MSTR: Master Selection
0: Slave configuration
1: Master configuration
Notes: This bit should not be changed when communication is ongoing.
Not used in I
2
S mode
Bit1 CPOL: Clock Polarity
0: CK to 0 when idle
1: CK to 1 when idle
Notes: This bit should not be changed when communication is ongoing.
Not used in I
2
S mode
Bit 0 CPHA: Clock Phase
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
Notes: This bit should not be changed when communication is ongoing.
Not used in I
2
S mode