ST STM32L4 5 Series User Manual

DocID024597 Rev 5 1103/1830
RM0351 General-purpose timers (TIM15/TIM16/TIM17)
1133
32.5.9 TIM15 counter (TIM15_CNT)
Address offset: 0x24
Reset value: 0x0000 0000
32.5.10 TIM15 prescaler (TIM15_PSC)
Address offset: 0x28
Reset value: 0x0000
32.5.11 TIM15 auto-reload register (TIM15_ARR)
Address offset: 0x2C
Reset value: 0xFFFF
31 30 29 28 27 26 25 24 23 22 21 20
19 18 17 16
UIF
CPY
Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res
r
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CNT[15:0]
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Bit 31 UIFCPY: UIF Copy
This bit is a read-only copy of the UIF bit in the TIMx_ISR register.
Bits 30:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value
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PSC[15:0]
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Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency (CK_CNT) is equal to f
CK_PSC
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger
controller when configured in “reset mode”).
1514131211109876543210
ARR[15:0]
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Bits 15:0 ARR[15:0]: Prescaler value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 32.4.1: Time-base unit on page 1057 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.

ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English