DocID024597 Rev 5 1183/1830
RM0351 System window watchdog (WWDG)
1185
Refer to the datasheet for the minimum and maximum values of the t
WWDG
.
37.3.5 Debug mode
When the microcontroller enters debug mode (Cortex
®
-M4 core halted), the WWDG counter
either continues to work normally or stops, depending on DBG_WWDG_STOP
configuration bit in DBG module. For more details, refer to Section 48.16.2: Debug support
for timers, RTC, watchdog, bxCAN and I2C.
37.4 WWDG registers
Refer to Section 1.1 on page 67 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
37.4.1 Control register (WWDG_CR)
Address offset: 0x00
Reset value: 0x0000 007F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. WDGA T[6:0]
rs rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 WDGA: Activation bit
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
These bits contain the value of the watchdog counter. It is decremented every (4096 x
2
WDGTB
[1:0]
) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6
becomes cleared).
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