DocID024597 Rev 5 1297/1830
RM0351 Inter-integrated circuit (I2C) interface
1301
39.7.8 Interrupt clear register (I2C_ICR)
Address offset: 0x1C
Reset value: 0x0000 0000
Access: No wait states
Bit 2 RXNE: Receive data register not empty (receivers)
This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is
ready to be read. It is cleared when I2C_RXDR is read.
Note: This bit is cleared by hardware when PE=0.
Bit 1 TXIS: Transmit interrupt status (transmitters)
This bit is set by hardware when the I2C_TXDR register is empty and the data to be
transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be
sent is written in the I2C_TXDR register.
This bit can be written to ‘1’ by software when NOSTRETCH=1 only, in order to generate a
TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1).
Note: This bit is cleared by hardware when PE=0.
Bit 0 TXE: Transmit data register empty (transmitters)
This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next
data to be sent is written in the I2C_TXDR register.
This bit can be written to ‘1’ by software in order to flush the transmit data register I2C_TXDR.
Note: This bit is set by hardware when PE=0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res.
ALERT
CF
TIM
OUTCF
PECCF OVRCF
ARLO
CF
BERR
CF
Res. Res.
STOP
CF
NACK
CF
ADDR
CF
Res. Res. Res.
wwwwww www
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 ALERTCF: Alert flag clear
Writing 1 to this bit clears the ALERT flag in the I2C_ISR register.
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Please refer to Section 39.3: I2C implementation.
Bit 12 TIMOUTCF: Timeout detection flag clear
Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register.
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Please refer to Section 39.3: I2C implementation.
Bit 11 PECCF: PEC Error flag clear
Writing 1 to this bit clears the PECERR flag in the I2C_ISR register.
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Please refer to Section 39.3: I2C implementation.
Bit 10 OVRCF: Overrun/Underrun flag clear
Writing 1 to this bit clears the OVR flag in the I2C_ISR register.
To Next Page
Loading...
Need help?
General
