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Universal synchronous asynchronous receiver transmitter (USART) RM0351

1366/1830 DocID024597 Rev 5

Bit 12 EOBCF: End of block clear flag

Writing 1 to this bit clears the EOBF flag in the USART_ISR register.

Note: If the USART does not support Smartcard mode, this bit is reserved and forced by

hardware to ‘0’. Please refer to Section 40.4: USART implementation on page 1304.

Bit 11 RTOCF: Receiver timeout clear flag

Writing 1 to this bit clears the RTOF flag in the USART_ISR register.

Note: If the USART does not support the Receiver timeout feature, this bit is reserved and

forced by hardware to ‘0’. Please refer to Section 40.4: USART implementation on

page 1304.

Bit 10 Reserved, must be kept at reset value.

Bit 9 CTSCF: CTS clear flag

Writing 1 to this bit clears the CTSIF flag in the USART_ISR register.

Note: If the hardware flow control feature is not supported, this bit is reserved and forced by

hardware to ‘0’. Please refer to Section 40.4: USART implementation on page 1304.

Bit 8 LBDCF: LIN break detection clear flag

Writing 1 to this bit clears the LBDF flag in the USART_ISR register.

Note: If LIN mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please

refer to Section 40.4: USART implementation on page 1304.

Bit 7 TCBGTCF: Transmission completed before guard time clear flag

Writing 1 to this bit clears the TCBGT flag in the USART_ISR register.

Note: If the USART does not support SmartCard mode, this bit is reserved and forced by

hardware to 0. Please refer to Section 40.4: USART implementation on page 1304).

Note: This bit is available on STM32L496xx/4A6xx devices only

Bit 6 TCCF: Transmission complete clear flag

Writing 1 to this bit clears the TC flag in the USART_ISR register.

Bit 5 Reserved, must be kept at reset value.

Bit 4 IDLECF: Idle line detected clear flag

Writing 1 to this bit clears the IDLE flag in the USART_ISR register.

Bit 3 ORECF: Overrun error clear flag

Writing 1 to this bit clears the ORE flag in the USART_ISR register.

Bit 2 NCF: Noise detected clear flag

Writing 1 to this bit clears the NF flag in the USART_ISR register.

Bit 1 FECF: Framing error clear flag

Writing 1 to this bit clears the FE flag in the USART_ISR register.

Bit 0 PECF: Parity error clear flag

Writing 1 to this bit clears the PE flag in the USART_ISR register.

ST STM32L4 5 Series User Manual

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