DocID024597 Rev 5 1695/1830
RM0351 USB on-the-go full-speed (OTG_FS)
1774
47.15.34 OTG device status register (OTG_DSTS)
Address offset: 0x808
Reset value: 0x0000 0010
This register indicates the status of the core with respect to USB-related events. It must be
read on interrupts from the device all interrupts (OTG_DAINT) register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. DEVLNSTS FNSOF
r rrrrrr
1514131211109876543210
FNSOF Res. Res. Res. Res. EERR ENUMSPD
SUSP
STS
rrrrrrrr rrrr
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:22 DEVLNSTS: Device line status
Indicates the current logic level USB data lines.
Bit [23]: Logic level of D+
Bit [22]: Logic level of D-
Bits 21:8 FNSOF: Frame number of the received SOF
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 EERR: Erratic error
The core sets this bit to report any erratic errors.
Due to erratic errors, the
OTG_FS controller goes into Suspended state and an interrupt is
generated to the application with Early suspend bit of the OTG_GINTSTS register (ESUSP
bit in OTG_GINTSTS). If the early suspend is asserted due to an erratic error, the application
can only perform a soft disconnect recover.
Bits 2:1 ENUMSPD: Enumerated speed
Indicates the speed at which the
OTG_FS controller has come up after speed detection
through a chirp sequence.
01: Reserved
10: Reserved
11: Full speed (PHY clock is running at 48 MHz)
Others: reserved
Bit 0 SUSPSTS: Suspend status
In device mode, this bit is set as long as a Suspend condition is detected on the USB. The
core enters the Suspended state when there is no activity on the USB data lines for a period
of 3 ms. The core comes out of the suspend:
– When there is an activity on the USB data lines
– When the application writes to the Remote wakeup signaling bit in the OTG_DCTL register
(RWUSIG bit in OTG_DCTL).
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