ST STM32L4 5 Series User Manual

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RM0351 Quad-SPI interface (QUADSPI)
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17.4.11 QUADSPI usage
The operating mode is selected using FMODE[1:0] (QUADSPI_CCR[27:26]).
Indirect mode procedure
When FMODE is programmed to 00, indirect write mode is selected and data can be sent to
the Flash memory. With FMODE = 01, indirect read mode is selected where data can be
read from the Flash memory.
When the QUADSPI is used in indirect mode, the frames are constructed in the following
way:
1. Specify a number of data bytes to read or write in the QUADSPI_DLR.
2. Specify the frame format, mode and instruction code in the QUADSPI_CCR.
3. Specify optional alternate byte to be sent right after the address phase in the
QUADSPI_ABR.
4. Specify the operating mode in the QUADSPI_CR. If FMODE = 00 (indirect write mode)
and DMAEN = 1, then QUADSPI_AR should be specified before QUADSPI_CR,
because otherwise QUADSPI_DR might be written by the DMA before QUADSPI_AR
is updated (if the DMA controller has already been enabled)
5. Specify the targeted address in the QUADSPI_AR.
6. Read/Write the data from/to the FIFO through the QUADSPI_DR.
When writing the control register (QUADSPI_CR) the user specifies the following settings:
• The enable bit (EN) set to ‘1’
• The DMA enable bit (DMAEN) for transferring data to/from RAM
• Timeout counter enable bit (TCEN)
• Sample shift setting (SSHIFT)
• FIFO threshold level (FTRHES) to indicate when the FTF flag should be set
• Interrupt enables
• Automatic polling mode parameters: match mode and stop mode (valid when
FMODE = 11)
• Clock prescaler
When writing the communication configuration register (QUADSPI_CCR) the user specifies
the following parameters:
• The instruction byte through the INSTRUCTION bits
• The way the instruction has to be sent through the IMODE bits (1/2/4 lines)
• The way the address has to be sent through the ADMODE bits (None/1/2/4 lines)
• The address size (8/16/24/32-bit) through the ADSIZE bits
• The way the alternate bytes have to be sent through the ABMODE (None/1/2/4 lines)
• The alternate bytes number (1/2/3/4) through the ABSIZE bits
• The presence or not of dummy bytes through the DBMODE bit
• The number of dummy bytes through the DCYC bits
• The way the data have to be sent/received (None/1/2/4 lines) through the DMODE bits
If neither the address register (QUADSPI_AR) nor the data register (QUADSPI_DR) need to
be updated for a particular command, then the command sequence starts as soon as

ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English