Analog-to-digital converters (ADC) RM0351
518/1830 DocID024597 Rev 5
18.4.12 Channel-wise programmable sampling time (SMPR1, SMPR2)
Before starting a conversion, the ADC must establish a direct connection between the
voltage source under measurement and the embedded sampling capacitor of the ADC. This
sampling time must be enough for the input voltage source to charge the embedded
capacitor to the input voltage level.
Each channel can be sampled with a different sampling time which is programmable using
the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. It is therefore possible to
select among the following sampling time values:
• SMP = 000: 2.5 ADC clock cycles
• SMP = 001: 6.5 ADC clock cycles
• SMP = 010: 12.5 ADC clock cycles
• SMP = 011: 24.5 ADC clock cycles
• SMP = 100: 47.5 ADC clock cycles
• SMP = 101: 92.5 ADC clock cycles
• SMP = 110: 247.5 ADC clock cycles
• SMP = 111: 640.5 ADC clock cycles
The total conversion time is calculated as follows:
T
CONV
= Sampling time + 12.5 ADC clock cycles
Example:
With F
ADC_CLK
= 80 MHz and a sampling time of 2.5 ADC clock cycles:
T
CONV
= (2.5 + 12.5) ADC clock cycles = 15 ADC clock cycles = 187.5 ns (for fast
channels)
The ADC notifies the end of the sampling phase by setting the status bit EOSMP (only for
regular conversion).
Constraints on the sampling time for fast and slow channels
For each channel, SMP[2:0] bits must be programmed to respect a minimum sampling time
as specified in the ADC characteristics section of the datasheets.
I/O analog switches voltage booster
The I/O analog switches resistance increases when the V
DDA
voltage is too low. This
requires to have the sampling time adapted accordingly (cf datasheet for electrical
characteristics). This resistance can be minimized at low V
DDA
by enabling an internal
voltage booster with BOOSTEN bit in the SYSCFG_CFGR1 register.
SMPPLUS control bit
When a sampling time of 2.5 ADC clock cycles is selected, the total conversion time
becomes 15 cycles in 12-bit mode. If the dual interleaved mode is used (see Section :
Interleaved mode with independent injected), the sampling interval cannot be equal to the
value specified since an even number of cycles is required for the conversion. The
SMPPLUS bit can be used to change the sampling time 2.5 ADC clock cycles into 3.5 ADC
clock cycles. In this way, the total conversion time becomes 16 clock cycles, thus making
possible to interleave every 8 cycles.
To Next Page
Loading...
Need help?
General
