Analog-to-digital converters (ADC) RM0351
574/1830 DocID024597 Rev 5
Note: When using MDMA mode, the user must take care to configure properly the duration of the
master and slave conversions so that a DMA request is generated and served for reading
both data (master + slave) before a new conversion is available.
• MDMA=0b11: This mode is similar to the MDMA=0b10. The only differences are that
on each DMA request (two data items are available), two bytes representing two ADC
converted data items are transferred as a half-word.
This mode is used in interleaved and regular simultaneous mode when resolution is 6-
bit or when resolution is 8-bit and data is not signed (offsets must be disabled for all the
involved channels).
Example:
Interleaved dual mode: a DMA request is generated each time 2 data items are
available:
1st DMA request: ADC_CDR[15:0] = SLV_ADC_DR[7:0] | MST_ADC_DR[7:0]
2nd DMA request: ADC_CDR[15:0] = SLV_ADC_DR[7:0] | MST_ADC_DR[7:0]
Overrun detection
In dual ADC mode (when DUAL[4:0] is not equal to b00000), if an overrun is detected on
one of the ADCs, the DMA requests are no longer issued to ensure that all the data
transferred to the RAM are valid (this behavior occurs whatever the MDMA configuration). It
may happen that the EOC bit corresponding to one ADC remains set because the data
register of this ADC contains valid data.
DMA one shot mode/ DMA circular mode when MDMA mode is selected
When MDMA mode is selected (0b10 or 0b11), bit DMACFG of the ADC_CCR register must
also be configured to select between DMA one shot mode and circular mode, as explained
in section Section : Managing conversions using the DMA (bits DMACFG of master and
slave ADC_CFGR are not relevant).
Stopping the conversions in dual ADC modes
The user must set the control bits ADSTP/JADSTP of the master ADC to stop the
conversions of both ADC in dual ADC mode. The other ADSTP control bit of the slave ADC
has no effect in dual ADC mode.
Once both ADC are effectively stopped, the bits ADSTART/JADSTART of the master and
slave ADCs are both cleared by hardware.
DFSDM mode in dual ADC interleaved mode
In dual ADC interleaved modes (DUAL[4:0] = 00011 or DUAL[4:0] = 00111), the ADC
conversion results can be transferred directly to the DFSDM.
The DFSDM mode is enabled by setting DFSDMCFG bits to 1 in the master ADC
ADC_CFGR register.
The ADC transfers alternatively the 16 least significant bits of the regular data register from
the master and the slave converter to a single channel of the DFSDM. Each transfer resets
the EOC flag of each channel once the transfer is complete.
To use this mode, the application software must configure MDMA[1:0] bits of ADC_CCR to
‘01’.
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