DocID024597 Rev 5 595/1830
RM0351 Analog-to-digital converters (ADC)
614
18.6.8 ADC watchdog threshold register 1 (ADC_TR1)
Address offset: 0x20
Reset value: 0x0FFF 0000
18.6.9 ADC watchdog threshold register 2 (ADC_TR2)
Address offset: 0x24
Reset value: 0x00FF 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. HT1[11:0]
1514131211109876543210
Res. Res. Res. Res. LT1[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog 1.
Refer to Section 18.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT1[11:0]: Analog watchdog 1 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog 1.
Refer to Section 18.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. HT2[7:0]
rw rw rw rw rw rw rw rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. LT2[7:0]
rw rw rw rw rw rw rw rw
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