Analog-to-digital converters (ADC) RM0351
600/1830 DocID024597 Rev 5
18.6.14 ADC regular sequence register 4 (ADC_SQR4)
Address offset: 0x3C
Reset value: 0x0000 0000
18.6.15 ADC regular Data Register (ADC_DR)
Address offset: 0x40
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. SQ16[4:0] Res. SQ15[4:0]
rw rw rw rw rw rw rw rw rw rw
Bits 31:11 Reserved, must be kept at reset value.
Bits 10:6 SQ16[4:0]: 16th conversion in regular sequence
These bits are written by software with the channel number (0..18) assigned as the 16th in
the regular conversion sequence.
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).
Bit 5 Reserved, must be kept at reset value.
Bits 4:0 SQ15[4:0]: 15th conversion in regular sequence
These bits are written by software with the channel number (0..18) assigned as the 15th in
the regular conversion sequence.
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
RDATA[15:0]
rrrrrrrrrrrrrrrr
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 RDATA[15:0]: Regular Data converted
These bits are read-only. They contain the conversion result from the last converted regular channel.
The data are left- or right-aligned as described in Section 18.4.26: Data management.
To Next Page
Loading...
Need help?
General
