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RM0351 Hash processor (HASH)
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29 Hash processor (HASH)
This section applies to STM32L496xx/4A6xx devices.
29.1 Introduction
The hash processor is a fully compliant implementation of the secure hash algorithm
(SHA-1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and
the HMAC (keyed-hash message authentication code) algorithm suitable for a variety of
applications. HMAC algorithms provide a way of authenticating messages by means of hash
functions. It consist in calling the SHA-1, SHA-224, SHA-256 or MD5 hash function twice.
The hash processor computes message digests (160 bits for the SHA-1 algorithm, 256 bits
for the SHA-256 algorithm and 224 bits for the SHA-224 algorithm,128 bits for the MD5
algorithm) for messages of up to (2
64
– 1) bits.
29.2 HASH main features
• Suitable for data authentication applications, compliant with:
– FIPS PUB 180-1 (Federal Information Processing Standards Publication 180-1)
Secure Hash Standard specifications (SHA-1)
– FIPS PUB 180-2 (Federal Information Processing Standards Publication 180-2)
Secure Hash Standard specifications (SHA-224 and SHA-256)
– Internet Engineering Task Force (IETF) Request For Comments RFC 1321 MD5
Message-Digest Algorithm
– Internet Engineering Task Force (IETF) Request For Comments RFC 2104
HMAC: Keyed-Hashing for Message Authentication
• Corresponding 32-bit words of the digest from consecutive message blocks are added
to each other to form the digest of the whole message
– Automatic 32-bit words swapping to comply with the internal little-endian
representation of the input bit-string
– Word swapping supported: bits, bytes, half-words and 32-bit words
• Automatic padding to complete the input bit string to fit digest minimum block size of
512 bits (16 × 32 bits)
• Single 32-bit input register associated to an internal input FIFO of sixteen 32-bit words,
corresponding to one block size
• Fast computation of SHA-1, SHA-224, SHA-256, and MD5
– 82 (respectively 66) clock cycles for processing one 512-bit block of data using
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