Intel Arria 10 User Manual

2.6.4.7.6. Speed Change Summary
Table 150. Speed Change Summary
Speed Change Speed Change Method Detailed Information
1GbE and 10GBASE-R Interface Signals • Refer to Dynamic Reconfiguration
Interface.
• Figure 77 on page 197
SGMII (10M, 100M and 1GbE) Avalon-MM bus Table 124 on page 160
1GbE, 10GBASE-R, and 10GBASE-R
with FEC
Avalon-MM bus Table 145 on page 182
Note: You can configure the static speed while generating the IP core using the IP Parameter
Editor.
Related Information
Dynamic Reconfiguration Interface on page 148
2.6.4.8. Creating a 1G/10GbE Design
Follow these steps to create a 1G/10GbE design using the 1G/10GbE PHY IP.
1. Generate the 1G/10GbE PHY with the required parameterization.
The 1G/10GbE PHY IP Core includes reconfiguration logic. This logic provides the
Avalon-MM interface that you can use to read and write to PHY registers. All read
and write operations must adhere to the Avalon specification.
2. Instantiate a reset controller using the Transceiver Reset Controller Intel FPGA IP
Core in the IP Catalog. Connect the power and reset signals between the 1G/
10GbE PHY and the reset controller.
3. Instantiate one TX PLL for the 1G data rate and one TX PLL for the 10G data rate.
Connect the high speed serial clock and PLL lock signals between 1G/10GbE PHY
and TX PLLs. You can use any combination of fPLLs, ATX, or CMU PLLs.
4.
Use the tx_pma_divclk from 1G/10GbE PHY or generate a fPLL to create the
156.25 MHz XGMII clock from the 10G reference clock.
No Memory Initialization Files (.mif) are required for the 1G/10GbE design in Arria
10 devices.
5. Complete the design by creating a top level module to connect all the IP (1G/
10GbE PHY IP, PLL IP and Reset Controller) blocks.
Related Information
• fPLL on page 359
• CMU PLL on page 368
• ATX PLL on page 350
• Using the Transceiver PHY Reset Controller on page 433
• 1G/10GbE PHY Functional Description on page 166
2.6.4.9. Design Guidelines
Consider the following guidelines while designing with 1G/10GbE PHY.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
196

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex