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ST STM32F102 series User Manual

ST STM32F102 series
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Contents RM0008
4/690
6.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.2.7 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.2.8 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.2.9 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.2.10 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3.2 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . . 78
6.3.3 Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.4 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . . 83
6.3.5 APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . . 85
6.3.6 AHB Peripheral Clock enable register (RCC_AHBENR) . . . . . . . . . . . . 87
6.3.7 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . . 88
6.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . . 90
6.3.9 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . . 93
6.3.10 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.3.11 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7 General-purpose and alternate-function I/Os (GPIOs and AFIOs) . . . 97
7.1 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.1.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.1.2 Atomic bit set or reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.1.3 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.1.4 Alternate functions (AF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.1.5 Software remapping of I/O alternate functions . . . . . . . . . . . . . . . . . . 100
7.1.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.1.7 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.1.8 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.1.9 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.1.10 Analog input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.2 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.2.1 Port configuration register low (GPIOx_CRL) (x=A..G) . . . . . . . . . . . . 105
7.2.2 Port configuration register high (GPIOx_CRH) (x=A..G) . . . . . . . . . . . 106
7.2.3 Port input data register (GPIOx_IDR) (x=A..G) . . . . . . . . . . . . . . . . . . 107
7.2.4 Port output data register (GPIOx_ODR) (x=A..G) . . . . . . . . . . . . . . . . 107
7.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..G) . . . . . . . . . . . . . . . 108
7.2.6 Port bit reset register (GPIOx_BRR) (x=A..G) . . . . . . . . . . . . . . . . . . . 108

Table of Contents

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ST STM32F102 series Specifications

General IconGeneral
BrandST
ModelSTM32F102 series
CategoryMicrocontrollers
LanguageEnglish

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