RM0008 USB full speed device interface (USB)
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Bit 15 CTR_RX: Correct Transfer for reception
This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this
endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set
accordingly, a generic interrupt condition is generated together with the endpoint related interrupt
condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be
determined from the SETUP bit described below.
A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually
transferred, as in the case of protocol errors or data toggle mismatches.
This bit is read/write but only ‘0’ can be written, writing 1 has no effect.
Bit 14 DTOG_RX: Data Toggle, for reception transfers
If the endpoint is not Isochronous, this bit contains the expected value of the data toggle bit
(0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit, when the
ACK handshake is sent to the USB host, following a data packet reception having a matching data
PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a
SETUP PID addressed to this endpoint.
If the endpoint is using the double-buffering feature this bit is used to support packet buffer swapping
too (Refer to Section 20.4.3: Double-buffered endpoints).
If the endpoint is Isochronous, this bit is used only to support packet buffer swapping since no data
toggling is used for this sort of endpoints and only DATA0 packet are transmitted (Refer to
Section 20.4.4: Isochronous transfers). Hardware toggles this bit just after the end of data packet
reception, since no handshake is used for isochronous transfers.
This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is
not a control one) or to force specific data toggle/packet buffer usage. When the application software
writes ‘0’, the value of DTOG_RX remains unchanged, while writing ‘1’ makes the bit value toggle.
This bit is read/write but it can be only toggled by writing 1.
Bits 13:12 STAT_RX [1:0]: Status bits, for reception transfers
These bits contain information about the endpoint status, which are listed in Table 137: Reception
status encoding on page 493.These bits can be toggled by software to initialize their value. When
the application software writes ‘0’, the value remains unchanged, while writing ‘1’ makes the bit
value toggle. Hardware sets the STAT_RX bits to NAK when a correct transfer has occurred
(CTR_RX=1) corresponding to a OUT or SETUP (control only) transaction addressed to this
endpoint, so the software has the time to elaborate the received data before it acknowledge a new
transaction
Double-buffered bulk endpoints implement a special transaction flow control, which control the
status based upon buffer availability condition (Refer to Section 20.4.3: Double-buffered endpoints).
If the endpoint is defined as Isochronous, its status can be only “VALID” or “DISABLED”, so that the
hardware cannot change the status of the endpoint after a successful transaction. If the software
sets the STAT_RX bits to ‘STALL’ or ‘NAK’ for an Isochronous endpoint, the USB peripheral behavior
is not defined. These bits are read/write but they can be only toggled by writing ‘1’.
Bit 11 SETUP: Setup transaction completed
This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP.
This bit changes its value only for control endpoints. It must be examined, in the case of a successful
receive transaction (CTR_RX event), to determine the type of transaction occurred. To protect the
interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept
frozen while CTR_RX bit is at 1; its state changes when CTR_RX is at 0. This bit is read-only.
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