USB full speed device interface (USB) RM0008
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Bits 10:9 EP_TYPE[1:0]: Endpoint type
These bits configure the behavior of this endpoint as described in Table 138: Endpoint type
encoding on page 493. Endpoint 0 must always be a control endpoint and each USB function must
have at least one control endpoint which has address 0, but there may be other control endpoints if
required. Only control endpoints handle SETUP transactions, which are ignored by endpoints of
other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint is
defined as NAK, the USB peripheral will not answer, simulating a receive error, in the receive
direction when a SETUP transaction is received. If the control endpoint is defined as STALL in the
receive direction, then the SETUP packet will be accepted anyway, transferring data and issuing the
CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint
is a control one.
Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature
available using the EP_KIND configuration bit.
The usage of Isochronous endpoints is explained in Section 20.4.4: Isochronous transfers
Bit 8 EP_KIND: Endpoint Kind
The meaning of this bit depends on the endpoint type configured by the EP_TYPE bits. Table 1 39
summarizes the different meanings.
DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk
endpoint. The usage of double-buffered bulk endpoints is explained in Section 20.4.3: Double-
buffered endpoints.
STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in
this case all OUT transactions containing more than zero data bytes are answered ‘STALL’ instead of
‘ACK’. This bit may be used to improve the robustness of the application to protocol errors during
control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset,
OUT transactions can have any number of bytes, as required.
Bit 7 CTR_TX: Correct Transfer for transmission
This bit is set by the hardware when an IN transaction is successfully completed on this endpoint;
the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a
generic interrupt condition is generated together with the endpoint related interrupt condition, which
is always activated.
A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually
transferred, as in the case of protocol errors or data toggle mismatches.
This bit is read/write but only ‘0’ can be written.
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