RM0008 Controller area network (bxCAN)
523/690
CAN receive FIFO 0 register (CAN_RF0R)
Address offset: 0x0C
Reset value: 0x00
Bit 8 RQCP1: Request Completed Mailbox1
Set by hardware when the last request (transmit or abort) has been performed.
Cleared by software writing a “1” or by hardware on transmission request (TXRQ1 set in CAN_TI1R
register).
Clearing this bit clears all the status bits (TXOK1, ALST1 and TERR1) for Mailbox 1.
Bit 7 ABRQ0: Abort Request for Mailbox0
Set by software to abort the transmission request for the corresponding mailbox.
Cleared by hardware when the mailbox becomes empty.
Setting this bit has no effect when the mailbox is not pending for transmission.
Bits 6:4 Reserved, forced by hardware to 0.
Bit 3 TERR0: Transmission Error of Mailbox0
This bit is set when the previous TX failed due to an error.
Bit 2 ALST0: Arbitration Lost for Mailbox0
This bit is set when the previous TX failed due to an arbitration lost.
Bit 1 TXOK0: Transmission OK of Mailbox0
The hardware updates this bit after each transmission attempt.
0: The previous transmission failed
1: The previous transmission was successful
This bit is set by hardware when the transmission request on mailbox 1 has been completed
successfully. Please refer to Figure 197
Bit 0 RQCP0: Request Completed Mailbox0
Set by hardware when the last request (transmit or abort) has been performed.
Cleared by software writing a “1” or by hardware on transmission request (TXRQ0 set in CAN_TI0R
register).
Clearing this bit clears all the status bits (TXOK0, ALST0 and TERR0) for Mailbox 0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109876543210
Reserved
RFOM
0
FOVR
0
FULL0
Res.
FMP0[1:0]
Res. rs rc_w1 rc_w1 r r
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