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ST STM32F102 series - Page 532

ST STM32F102 series
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Controller area network (bxCAN) RM0008
532/690
Receive FIFO mailbox data length control and time stamp register
(CAN_RDTxR) (x=0..1)
Address offsets: 0x1B4, 0x1C4
Reset value: 0xXX where X is undefined
Note: All RX registers are write protected.
Bit 2 IDE: Identifier Extension
This bit defines the identifier type of message in the mailbox.
0: Standard identifier.
1: Extended identifier.
Bit 1 RTR: Remote Transmission Request
0: Data frame
1: Remote frame
Bit 0 Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME[15:0]
rrrrrrrrrrrrrrrr
1514131211109876543210
FMI[7:0] Reserved DLC[3:0]
rrrrrrrr Res. rrrr
Bits 31:16 TIME[15:0]: Message Time Stamp
This field contains the 16-bit timer value captured at the SOF detection.
Bits 15:8 FMI[7:0]: Filter Match Index
This register contains the index of the filter the message stored in the mailbox passed through. For
more details on identifier filtering please refer to Section 21.4.4: Identifier filtering on page 508 -
Filter Match Index paragraph.
Bits 7:4 Reserved, forced by hardware to 0.
Bits 3:0 DLC[3:0]: Data Length Code
This field defines the number of data bytes a data frame contains (0 to 8). It is 0 in the case of a
remote frame request.

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