General-purpose timers (TIM15/TIM16/TIM17) RM0351
1088/1830 DocID024597 Rev 5
32.4.20 Timer synchronization (TIM15)
The TIMx timers are linked together internally for timer synchronization or chaining. Refer to
Section 32.4.20: Timer synchronization (TIM15) for details.
Note: The clock of the slave timer must be enabled prior to receive events from the master timer,
and must not be changed on-the-fly while triggers are received from the master timer.
32.4.21 Debug mode
When the microcontroller enters debug mode (Cortex
®
-M4 core halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to Section 48.16.2: Debug support for timers,
RTC, watchdog, bxCAN and I2C.
For safety purposes, when the counter is stopped (DBG_TIMx_STOP = 1), the outputs are
disabled (as if the MOE bit was reset). The outputs can either be forced to an inactive state
(OSSI bit = 1), or have their control taken over by the GPIO controller (OSSI bit = 0) to force
them to Hi-Z.
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