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SD/SDIO/MMC card host interface (SDMMC) RM0351

1560/1830 DocID024597 Rev 5

The behavior is to stop SDMMC_CK and freeze SDMMC state machines. The data transfer

is stalled while the FIFO is unable to transmit or receive data. Only state machines clocked

by SDMMCCLK are frozen, the APB2 interface is still alive. The FIFO can thus be filled or

emptied even if flow control is activated.

To enable HW flow control, the SDMMC_CLKCR[14] register bit must be set to 1. After reset

Flow Control is disabled.

45.8 SDMMC registers

The device communicates to the system via 32-bit-wide control registers accessible via

APB2.

45.8.1 SDMMC power control register (SDMMC_POWER)

Address offset: 0x00

Reset value: 0x0000 0000

Note: At least seven PCLK2 clock periods are needed between two write accesses to this register.

Note: After a data write, data cannot be written to this register for three SDMMCCLK clock periods

plus two PCLK2 clock periods.

45.8.2 SDMMC clock control register (SDMMC_CLKCR)

Address offset: 0x04

Reset value: 0x0000 0000

The SDMMC_CLKCR register controls the SDMMC_CK output clock.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PWRCTRL

rw rw

Bits 31:2 Reserved, must be kept at reset value.

[1:0] PWRCTRL: Power supply control bits.

These bits are used to define the current functional state of the card clock:

00: Power-off: the clock to card is stopped.

01: Reserved

10: Reserved power-up

11: Power-on: the card is clocked.

ST STM32L4 5 Series User Manual

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