DocID024597 Rev 5 1823/1830
RM0351 Revision history
1823
27-Feb-2017
5
(continued)
Section 40.8.8: Interrupt and status register
(USART_ISR), Table 240: USART register map and
reset values
LPUART:
Updated Section 41.4.11: Wakeup from Stop mode
using LPUART
SPI:
Updated Section 42.4.7: Configuration of SPI,
Section 42.4.14: CRC calculation, Section 42.6.6: SPI
Rx CRC register (SPIx_RXCRCR), Section 42.6.7: SPI
Tx CRC register (SPIx_TXCRCR)
SAI:
Updated Figure 459: Functional block diagram,
Section 43.3.8: SAI clock generator, Table 254:
Example of possible audio frequency sampling range
Added Section 43.3.2: SAI pins and internal signals
BxCAN:
Updated Section 46.9.4: CAN filter registers, Table 299:
bxCAN register map and reset values
Added Section : Dual CAN peripheral configuration,
Figure 502: Dual CAN block diagram
OTG_FS:
Updated Section 47.5.1: ID line detection, Figure 519:
USB_FS peripheral-only connection, Section 47.15.5:
OTG reset register (OTG_GRSTCTL),
Section 47.15.13: OTG core ID register (OTG_CID),
Section 47.15.32: OTG device configuration register
(OTG_DCFG), Section 47.15.53: OTG power and clock
gating control register (OTG_PCGCCTL), Table 309:
OTG_FS register map and reset values
DEBUG SUPPORT:
Updated Section 48.4.2: Flexible SWJ-DP pin
assignment, Section 48.6.1: MCU device ID code,
Section 48.16.4: Debug MCU APB1 freeze
register1(DBGMCU_APB1FZR1), Section 48.16.5:
Debug MCU APB1 freeze register 2
(DBGMCU_APB1FZR2), Table 323: Synchronous
TRACE pin assignment, Table 324: Flexible TRACE pin
assignment, Table 326: DBG register map and reset
values
DEVICE ELECTRONIC SIGNATURE:
Updated Section 49.3: Package data register
Table 327. Document revision history (continued)
Date Revision Changes
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