ST STM32L4 5 Series - Page 1822

Revision history RM0351
1822/1830 DocID024597 Rev 5
27-Feb-2017
5
(continued)
Section 24.4.6: Parallel data inputs, Section 24.4.13:
Data unit block
Added Section 24.3: DFSDM implementation,
Table 155: DFSDM break connection, Figure 164: Input
channel pins redirection
RNG:
Updated Section 27.3.5: RNG operation, Section 27.3.7:
Error management, Section 27.8.1: RNG control register
(RNG_CR), Section 27.8.2: RNG status register
(RNG_SR)
Added Section 27.3.1: RNG block diagram,
Section 27.3.2: RNG internal signals, Section 27.3.3:
Random number generation, Section 27.3.4: RNG
initialization, Section 27.3.6: RNG clocking,
Section 27.4: RNG low-power usage, Section 27.5:
RNG interrupts, Section 27.6: RNG processing time,
Section 27.7: Entropy source validation
AES:
Updated Figure 200: 128-bit block construction
according to the data type (continued), Figure 204:
Mode 4: key derivation and decryption with 128-bit key
length, Figure 205: DMA requests and data transfers
during Input phase (AES_IN), Figure 206: DMA requests
during Output phase (AES_OUT)
HASH: added Section 29: Hash processor (HASH)
TIM15/TIM16/TIM17:
Updated Section 32.4.21: Debug mode, Table 196:
Output control bits for complementary OCx and OCxN
channels with break feature (TIM15), Section 32.6.3:
TIM16/TIM17 DMA/interrupt enable register
(TIMx_DIER), Table 198: Output control bits for
complementary OCx and OCxN channels with break
feature (TIM16/17), Table 199: TIM16/TIM17 register
map and reset values
RTC:
Updated Figure 374: RTC block diagram
I2C:
Updated Table 215: STM32L496xx/4A6xx devices I2C
implementation, Section : Master communication
initialization (address phase), Table 229: Effect of low-
power modes on the I2C, Section 39.7.2: Control
register 2 (I2C_CR2), Section 39.7.3: Own address 1
register (I2C_OAR1), Section 39.7.4: Own address 2
register (I2C_OAR2)
Added Table 216: STM32L475xx/476xx/486xx devices
I2C implementation
USART:
Updated Section 40.4: USART implementation,
Section 40.5.13: USART Smartcard mode, Table 239:
USART interrupt requests, Section 40.8.3: Control
register 3 (USART_CR3)
Table 327. Document revision history (continued)
Date Revision Changes