DocID024597 Rev 5 1821/1830
RM0351 Revision history
1823
27-Feb-2017
5
(continued)
Table 83: FMC_BCRx bit fields, Table 86: FMC_BCRx
bit fields, Table 88: FMC_BCRx bit fields, Table 90:
FMC_BCRx bit fields, Section 16.5.6: NOR/PSRAM
controller registers
QUADSPI:
Updated Section 17.1: Introduction, Section 17.2:
QUADSPI main features, Section 17.4.4: QUADSPI
signal interface protocol modes, Section 17.4.7:
QUADSPI memory-mapped mode, Section 17.6.1:
QUADSPI control register (QUADSPI_CR), Table 101:
QUADSPI register map and reset values
Added Section 17.3: QUADSPI implementation,
Figure 59: QUADSPI block diagram when dual-flash
mode is enabled, Section 17.4.2: QUADSPI pins,
Section 17.4.5: QUADSPI indirect mode
ADC:
Updated Section 18.2: ADC main features, Figure 66:
ADC block diagram, Table 104: ADC pins,
Section 18.4.3: Clocks, Section 18.4.12: Channel-wise
programmable sampling time (SMPR1, SMPR2),
Table 107: ADC1, ADC2 and ADC3 - External triggers
for regular channels, Table 108: ADC1, ADC2 and
ADC3 - External trigger for injected channels, Figure 80:
Example of JSQR queue of context (sequence change),
Figure 81: Example of JSQR queue of context (trigger
change), Figure 84: Example of JSQR queue of context
with empty queue (case JQM=0), Figure 86: Flushing
JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing
conversion. Section 18.4.26: Data management,
Section 18.6.4: ADC configuration register
(ADC_CFGR), Section 18.6.6: ADC sample time
register 1 (ADC_SMPR1), Section 18.7.2: ADC common
control register (ADC_CCR)
Added Section 18.3: ADC implementation,
Section 18.4.27: Managing conversions using the
DFSDM, Section : DFSDM mode in dual ADC
interleaved mode, Section : DFSDM mode in dual ADC
simultaneous mode
DAC:
Updated Section 19.1: Introduction, Section 19.3.1:
DAC block diagram, Section 19.5.11: DUAL DAC 8-bit
right aligned data holding register (DAC_DHR8RD)
Added Table 122: DAC trigger selection
DCMI: Added Section 20: Digital camera interface
(DCMI)
DFSDM:
Updated Section 24.1: Introduction, Table 153: DFSDM
internal signals, Table 154: DFSDM triggers connection
Table 327. Document revision history (continued)
Date Revision Changes
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