Reset and clock control (RCC) RM0351
230/1830 DocID024597 Rev 5
Bit 17 PLLSAI1P: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock).
Set and cleared by software to control the frequency of the SAI1PLL output clock
PLLSAI1CLK. This output can be selected for SAI1 or SAI2. These bits can be written only if
SAI1PLL is disabled.
(When the PLLSAI1PDIV[4:0] is set to “00000” only on STM32L496xx/4A6xx
devices),PLLSAI1CLK output clock frequency = VCOSAI1 frequency / PLLSAI1P with
PLLSAI1P =7, or 17
0: PLLSAI1P = 7
1: PLLSAI1P = 17
Bit 16 PLLSAI1PEN: SAI1PLL PLLSAI1CLK output enable
Set and reset by software to enable the PLLSAI1CLK output of the SAI1PLL.
In order to save power, when the PLLSAI1CLK output of the SAI1PLL is not used, the value
of PLLSAI1PEN should be 0.
0: PLLSAI1CLK output disable
1: PLLSAI1CLK output enable
Bit 15 Reserved, must be kept at reset value.
Bits 14:8 PLLSAI1N[6:0]: SAI1PLL multiplication factor for VCO
Set and cleared by software to control the multiplication factor of the VCO. These bits can be
written only when the SAI1PLL is disabled.
VCOSAI1 output frequency = VCOSAI1 input frequency x PLLSAI1N
with 8 =< PLLSAI1N =< 86
0000000: PLLSAI1N = 0 wrong configuration
0000001: PLLSAI1N = 1 wrong configuration
...
0000111: PLLSAI1N = 7 wrong configuration
0001000: PLLSAI1N = 8
0001001: PLLSAI1N = 9
...
1010101: PLLSAI1N = 85
1010110: PLLSAI1N = 86
1010111: PLLSAI1N = 87 wrong configuration
...
1111111: PLLSAI1N = 127 wrong configuration
Caution: The software has to set correctly these bits to ensure that the VCO
output frequency is between 64 and 344 MHz.
Bits 7:0 Reserved, must be kept at reset value.
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