ST STM32L4 5 Series User Manual

DocID024597 Rev 5 229/1830
RM0351 Reset and clock control (RCC)
278
Bits 31:27 PLLSAI1PDIV[4:0]: PLLSAI1 division factor for PLLSAI1CLK (only on STM32L496xx/4A6xx
devices)
Set and cleared by software to control the SAI1 or SAI2 clock frequency. PLLSAI1CLK output
clock frequency = VCOSAI1 frequency / PLLPDIV.
00000: PLLSAI1CLK is controlled by the bit PLLP
00001: Reserved.
00010: PLLSAI1CLK = VCOSAI1 / 2
....
11111: PLLSAI1CLK = VCOSAI1 / 31
Bits 26:25 PLLSAI1R[1:0]: PLLSAI1 division factor for PLLADC1CLK (ADC clock)
Set and cleared by software to control the frequency of the SAI1PLL output clock
PLLADC1CLK. This output can be selected as ADC clock. These bits can be written only if
SAI1PLL is disabled.
PLLADC1CLK output clock frequency = VCOSAI1 frequency / PLLSAI1R with PLLSAI1R =
2, 4, 6, or 8
00: PLLSAI1R = 2
01: PLLSAI1R = 4
10: PLLSAI1R = 6
11: PLLSAI1R = 8
Bit 24 PLLSAI1REN: PLLSAI1 PLLADC1CLK output enable
Set and reset by software to enable the PLLADC1CLK output of the SAI1PLL (used as clock
for ADC).
In order to save power, when the PLLADC1CLK output of the SAI1PLL is not used, the value
of PLLSAI1REN should be 0.
0: PLLADC1CLK output disable
1: PLLADC1CLK output enable
Bit 23 Reserved, must be kept at reset value.
Bits 22:21 PLLSAI1Q[1:0]: SAI1PLL division factor for PLL48M2CLK (48 MHz clock)
Set and cleared by software to control the frequency of the SAI1PLL output clock
PLL48M2CLK. This output can be selected for USB, RNG, SDMMC (48 MHz clock). These
bits can be written only if SAI1PLL is disabled.
PLL48M2CLK output clock frequency = VCOSAI1 frequency / PLLQ with PLLQ = 2, 4, 6, or
8
00: PLLQ = 2
01: PLLQ = 4
10: PLLQ = 6
11: PLLQ = 8
Caution: The software has to set these bits correctly not to exceed 80 MHz on
this domain.
Bit 20 PLLSAI1QEN: SAI1PLL PLL48M2CLK output enable
Set and reset by software to enable the PLL48M2CLK output of the SAI1PLL.
In order to save power, when the PLL48M2CLK output of the SAI1PLL is not used, the value
of PLLSAI1QEN should be 0.
0: PLL48M2CLK output disable
1: PLL48M2CLK output enable
Bits 19:18 Reserved, must be kept at reset value.

ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English