ST STM32L4 5 Series - Page 332

Peripherals interconnect matrix RM0351
332/1830 DocID024597 Rev 5
The possible connections are given in:
• Section 30.4.21: TIM1 option register 1 (TIM1_OR1)
• Section 30.4.22: TIM8 option register 1 (TIM8_OR1)
• Section 30.4.26: TIM1 option register 2 (TIM1_OR2)
• Section 30.4.28: TIM8 option register 2 (TIM8_OR2)
• Section 31.4.19: TIM2 option register 1 (TIM2_OR1)
• Section 31.4.20: TIM3 option register 1 (TIM3_OR1)
• Section 31.4.21: TIM2 option register 2 (TIM2_OR2)
• Section 31.4.22: TIM3 option register 2 (TIM3_OR2)
• Section 32.3: TIM16/TIM17 main features
Active power mode
Run, Sleep, Low-power run, Low-power sleep.
10.3.14 From system errors to timers (TIM1/TIM8/TIM15/TIM16/TIM17)
Purpose
CSS, CPU hardfault, RAM parity error, FLASH ECC double error detection, PVD can
generate system errors in the form of timer break toward timers
(TIM1/TIM8/TIM15/TIM16/TIM17).
The purpose of the break function is to protect power switches driven by PWM signals
generated by the timers.
List of possible source of break are described in:
• Section 30.3.16: Using the break function (TIM1/TIM8)
• Section 32.4.13: Using the break function (TIM15/TIM16/TIM17)
• Figure 321: TIM15 block diagram
• Figure 322: TIM16/TIM17 block diagram
Active power mode
Run, Sleep, Low-power run, Low-power sleep.
10.3.15 From timers (TIM16/TIM17) to IRTIM
Purpose
General-purpose timer (TIM16/TIM17) output channel TIMx_OC1 are used to generate the
waveform of infrared signal output.
The functionality is described in Section 35: Infrared interface (IRTIM).
Active power mode
Run, Sleep, Low-power run, Low-power sleep.