DocID024597 Rev 5 333/1830
RM0351 Peripherals interconnect matrix
333
10.3.16 From ADC (ADC1/ADC2/ADC3) to DFSDM (only for
STM32L496xx/4A6xx devices)
Purpose
Up to 3 internal ADC results can be directly connected through a parallel bus to DFSDM
input in order to use DFSDM filtering capabilities.
The feature is described as part of DFSDM peripheral description in Section 24.4.6: Parallel
data inputs - Input from internal ADC
The possible connections are given in:
• Section 24.7.1: DFSDM channel configuration y register (DFSDM_CHyCFGR1)
(y=0..7)
– Bits 13:12 DATMPX[1:0]: Input data multiplexer for channel y
• Section 24.7.5: DFSDM channel data input register (DFSDM_CHyDATINR) (y=0..7)
– Bits 31:16 INDAT0[15:0]: Input data for channel y or channel y+1
– Bits 15:0 INDAT0[15:0]: Input data for channel y
Active power mode
Run, Sleep, Low-power run, Low-power sleep.
To Next Page
Loading...
Need help?
General
