RM0008 General-purpose timer (TIMx)
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Bits 9:8 CC2S[1:0]: Capture/Compare 2 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output.
01: CC2 channel is configured as input, IC2 is mapped on TI2.
10: CC2 channel is configured as input, IC2 is mapped on TI1.
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an
internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ’0’ in TIMx_CCER).
Bit 7 OC1CE: Output Compare 1Clear Enable
OC1CE: Output Compare 1 Clear Enable
0: OC1Ref is not affected by the ETRF input
1: OC1Ref is cleared as soon as a High level is detected on ETRF input
Bits 6:4 OC1M: Output Compare 1 Mode.
These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N
are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and
CC1NP bits.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter
TIMx_CNT has no effect on the outputs.
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else
inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as TIMx_CNT>TIMx_CCR1
else active (OC1REF=’1’).
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else
active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive.
Note 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in
TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
Note 2: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison
changes or when the output compare mode switches from “frozen” mode to “PWM” mode.
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