General-purpose timer (TIMx) RM0008
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Bit 3 OC1PE: Output Compare 1 Preload enable.
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is
taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
TIMx_CCR1 preload value is loaded in the active register at each update event.
Note 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in
TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
Note 2: The PWM mode can be used without validating the preload register only in one pulse mode
(OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output Compare 1 Fast enable.
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The
minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to
the compare level independently from the result of the comparison. Delay to sample the trigger input
and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured
in PWM1 or PWM2 mode.
Bits 1:0 CC1S: Capture/Compare 1 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ’0’ in TIMx_CCER).
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