Flexible static memory controller (FSMC) RM0008
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Note: PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these
memories issue the NWAIT signal during the whole latency phase to prolong the latency as
needed.
With PSRAMs (CRAMs) the filed DATLAT must be set to 0, so that the FSMC exits its
latency phase soon and starts sampling NWAIT from memory, then starts to read or write
when the memory is ready.
This method can be used also with the latest generation of synchronous Flash memories
that issue the NWAIT signal, unlike older Flash memories (check the datasheet of the
specific Flash memory being used).
Bits 15:8 DATAST: Data-phase duration.
These bits are written by software to define the duration of the data phase (refer to
Figure 157 to Figure 169), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash
accesses:
0000 0000: DATAST phase duration = 1 × HCLK clock cycle
...
0000_1111: DATAST phase duration = 16 × HCLK clock cycles (default value after reset)
Bits 7:4 ADDHLD: Address-hold phase duration.
These bits are written by software to define the duration of the address hold phase (refer to
Figure 166 to Figure 169), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash
accesses:
0000: ADDHLD phase duration = 1 × HCLK clock cycle
...
1111: ADDHLD phase duration = 16 × HCLK clock cycles (default value after reset)
Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is
always 1 Flash clock period duration.
Bits 3:0 ADDSET: Address setup phase duration.
These bits are written by software to define the duration of the address setup phase in HCLK
cycles (refer to Figure 166 to Figure 169), used in SRAMs, ROMs and asynchronous
multiplexed NOR Flash:
0000: ADDSET phase duration = 1 × HCLK clock cycle
...
1111: ADDSET phase duration = 16 × HCLK clock cycles (default value after reset)
Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is
always 1 Flash clock period duration.
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