RM0440 Rev 4 1045/2126
RM0440 High-resolution timer (HRTIM)
1083
27.5.61 HRTIM burst mode compare register (HRTIM_BMCMPR)
Address offset: 0x3A8
Reset value: 0x0000 0000
27.5.62 HRTIM burst mode period register (HRTIM_BMPER)
Address offset: 0x3AC
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
BMCMP[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 BMCMP[15:0]: Burst mode compare value
Defines the number of periods during which the selected timers are in idle state.
This register holds either the content of the preload register or the content of the active register if the
preload is disabled.
Note: BMCMP[15:0] cannot be set to 0x0000 when using the f
HRTIM
clock without a prescaler as the
burst mode clock source (BMCLK[3:0] = 1010 and BMPRESC[3:0] = 0000).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
BMPER[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 BMPER[15:0]: Burst mode period
Defines the burst mode repetition period.
This register holds either the content of the preload register or the content of the active register if
preload is disabled.
Note: The BMPER[15:0] must not be null when the burst mode is enabled.
To Next Page
Loading...
Need help?
General
