RM0440 Rev 4 521/2126
RM0440 Flexible static memory controller (FSMC)
571
19.6.1 External memory interface signals
Table 124, Table 125 and Table 126 list the signals that are typically used to interface with
NOR Flash memory, SRAM and PSRAM.
Note: The prefix “N” identifies the signals that are active low.
NOR Flash memory, non-multiplexed I/Os
The maximum capacity is 512 Mbits (26 address lines).
Table 123. Programmable NOR/PSRAM access parameters
Parameter Function Access mode Unit Min. Max.
Address
setup
Duration of the address
setup phase
Asynchronous
AHB clock cycle
(HCLK)
015
Address hold
Duration of the address hold
phase
Asynchronous,
muxed I/Os
AHB clock cycle
(HCLK)
115
NBL setup
Duration of the byte lanes
setup phase
Asynchronous
AHB clock cycle
(HCLK)
03
Data setup
Duration of the data setup
phase
Asynchronous
AHB clock cycle
(HCLK)
1256
Data hold
Duration of the data hold
phase
Asynchronous
AHB clock cycle
(HCLK)
03
Bust turn
Duration of the bus
turnaround phase
Asynchronous and
synchronous read
/ write
AHB clock cycle
(HCLK)
015
Clock divide
ratio
Number of AHB clock cycles
(HCLK) to build one memory
clock cycle (CLK)
Synchronous
AHB clock cycle
(HCLK)
2 16
Data latency
Number of clock cycles to
issue to the memory before
the first data of the burst
Synchronous
Memory clock
cycle (CLK)
2 17
Table 124. Non-multiplexed I/O NOR Flash memory
FMC signal name I/O Function
CLK O Clock (for synchronous access)
A[25:0] O Address bus
D[15:0] I/O Bidirectional data bus
NE[x] O Chip select, x = 1..4
NOE O Output enable
NWE O Write enable
NL(=NADV) O
Latch enable (this signal is called address
valid, NADV, by some NOR Flash devices)
NWAIT I NOR Flash wait input signal to the FMC
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