ST STM32G471 User Manual

Embedded Flash memory (FLASH) for category 3 devices RM0440
136/2126 RM0440 Rev 4
3.7.8 Flash option register (FLASH_OPTR)
Address offset: 0x20
Reset value: 0xFXXX XXXX. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
Bit 22 SYSF_ECC: System Flash ECC fail
This bit indicates that the ECC error correction or double ECC error detection is
located in the System Flash.
Bit 21 BK_ECC: ECC fail bank
DBANK=1
This bit indicates which bank is concerned by the ECC error correction or by the
double ECC error detection.
0: bank 1
1: bank 2
DBANK=0
If SYSF_ECC is 1, it indicates which bank is concerned by the ECC error
If SYSF_ECC is 0, reserved, must be kept cleared.
Bits 20:19 Reserved, must be kept at reset value.
Bits 18:0 ADDR_ECC: ECC fail address
DBANK=0
This bit indicates which address in the Flash memory is concerned by the ECC
error correction or by the double ECC error detection.
DBANK=1
This bit indicates which address in the bank is concerned by the ECC error
correction or by the double ECC error detection.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. IRHEN
NRST_MODE
[1:0]
n
BOOT0
nSW
BOOT0
CCM
SRAM_
RST
SRAM
_PE
nBOOT
1
DBANK Res. BFB2
WWDG
_SW
IWGD_
STDBY
IWDG_
StOP
IWDG_
SW
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Res.
nRST_
SHDW
nRST_
STDBY
nRST_
STOP
Res. BOR_LEV[2:0] RDP[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English